Software-Only Value Speculation Scheduling

Recent research in value prediction, including several recent publications for MICRO, shows a surprising amount of predictability for the values produced by register-writing instructions. Several hardware based value predictor designs have been proposed to exploit this predictability by eliminating flow dependencies for highly predictable values. A hardware and software based technique, value speculation scheduling (VSS), combines static instruction level parallelism (ILP) scheduling techniques with dynamic value prediction hardware. This paper extends the previous work on VSS to a software-only based scheme for VSS, which we will call software value speculation scheduling (SVSS). The advantages of SVSS are that no instruction set architecture (ISA) extensions and no value prediction hardware is required. Therefore, SVSS is applicable to existing microarchitectures such as Intel's P6, Digital's Alpha, Sun's UltraSparc and IBM/Motorola's PowerPC. As with VSS, static ILP scheduling techniques are used for SVSS to speculate value dependent instructions by scheduling them above the instructions whose results they are dependent on. For SVSS, compiler generated instructions are used to produce value predictions in place of the prediction hardware of 2 VSS. These predictions allow the execution of speculated instructions to continue. Again, in the case of miss-predicted values, control flow is redirected to patch-up code so that execution can proceed with the correct results. In this paper, experiments for applying SVSS to select load instructions in the SPECint95 benchmarks are performed. Speedup of up to 8% has been shown for using SVSS. Empirical results on the software-only value predictability of loads, based on value profiling data, are also provided.